1. Field of the Invention
The present invention relates to a semiconductor circuit element for reducing undesirable charging effects, and in particular to a connection element of test structures for semiconductor circuits, such as test structures for a technological process control for measuring and evaluating technological and electrical parameters at specific technological points in time.
2. Description of the Related Art
As an example, during production of DRAM memory circuits, it is possible to monitor the quality of the gate oxides by means of measurements of the breakdown dielectric strength and the quality of poly-Si or Al interconnects with regard to the frequency of interruptions or short circuits as sampling in the manufacturing process. By utilizing special masks in the technological section patterning on one or more wafers, instead of the circuits, test structures are to be produced which have experienced identical treatment in all of the processing steps and, consequently, do not contain any further influencing variables. Another, equivalent possibility frequently used is to generate test structures in a dicing channel in-between the product chips, without wasting productive area.
A test structure for integrated circuits for monitoring insulation in integrated circuits and in which electrically conductive connections between insulation regions and substrate dopings and also the electrical insulation between insulation regions that are isolated from one another can be assessed during and after the conclusion of the wafer processing.
In order to be able to access the test structures, they have to be electrically connected to external (or off-wafer) evaluation circuits. Connection elements are required for this purpose. Connection elements of this type are known as so-called pads.
Pads of this type, by virtue of their physically required size, are significant antennas which may collect undesirable charges during the fabrication process, for example during plasma or implantation processes, and transfer them to test structures. Said charges may lead to damage to the gate oxide of transistor or gate oxide test structures. In practice, cases have become known in which a charging problem not relevant to the product has been simulated by the undesirable antenna effect of a pad. In order nevertheless to be able to expediently utilize the test structure, it is desirable to reduce the charge collected by the pad.